Check out our recent Nature paper for the most up-to-date results! https://www.nature.com/articles/s41586-022-04992-8.

In the news:
IEEE Spectrum: https://spectrum.ieee.org/ai-chip
Singularity Hub: https://singularityhub.com/2022/08/30/this-brain-inspired-chip-ups-ai-computing-efficiency-while-using-less-energy/
Stanford: https://news.stanford.edu/2022/08/18/new-chip-ramps-ai-computing-efficiency/?utm_source=dlvr.it&utm_medium=twitter
UCSD: https://jacobsschool.ucsd.edu/news/release/3499
The Register: https://www.theregister.com/2022/08/18/ai_cim_chip_for_edge_paper/
Independent: https://www.independent.co.uk/tech/ai-artificial-intelligence-chip-memory-ram-b2146974.html
The Sun: https://www.the-sun.com/tech/6022063/unprecedented-artificial-intelligence-breakthrough/
EE News: https://www.eenewseurope.com/en/48-core-neuromorphic-ai-chip-uses-resistive-memory/
Tech Xplore: https://techxplore.com/news/2022-08-neuromorphic-chip-ai-edge-small.html
Freethink: https://www.freethink.com/technology/ai-microchip
Guokr: https://www.guokr.com/article/462071

Weier Wan's PhD defense talk at Stanford University on Oct. 26, 2021

Performing ever-demanding AI tasks directly on the resource-constrained edge devices calls for unprecedented energy-efficiency of edge AI hardware. AI hardware today consumes most energy through data movement between separate compute and memory units. Compute-in-memory (CIM) architectures using Resistive RAM (RRAM) integrated on the CMOS logic platform overcome this challenge by performing computation directly within memory. However, the energy-efficiency benefit of CIM usually comes at the cost of functional flexibility and computational accuracy, hampering its practical use for many edge applications that require processing multiple modalities of sensory data (e.g. video, audio). Such trade-offs between efficiency, versatility and accuracy cannot be addressed by isolated improvements on any single layer of the design.

In this talk, we present our attempts to ameliorate this fundamental trade-off through a full-stack co-optimization between device, circuit, architecture, and algorithm. By integrating multiple innovations including a voltage-mode sensing scheme, a transposable neurosynaptic array architecture, and non-ideality-aware model training and fine-tuning techniques, we demonstrated two fully-integrated RRAM-CIM chips that simultaneously deliver a high degree of reconfigurability for diverse model architectures, record energy-efficiency compared to prior arts, and software-comparable inference accuracy measured across various AI benchmarks including image classification, speech recognition, and image recovery.